1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a high-output, high-frequency GaAs field effect transistor (FET).
2. Description of the Prior Art
To increase output from a high-output FET, its gate width must be increased. For this purpose, a comb-shaped gate structure (inter-digital structure) in which gate fingers are formed parallel to each other is employed. In particular, a PHS (Plated Heat Sink) structure is employed in which a thin chip is used, and a thick metal layer is formed on the lower surface of the chip in order to cope with an increase in amount of heat generated as a result of increase in output from the element or device. In this structure, however, warping of the chip poses a problem.
FIG. 1 is a plan view showing conventional high-output FETs. In the structure shown in FIG. 1, pluralities of gate electrodes 2, source electrodes 3, and drain electrodes 4 are alternately aligned in parallel with one another on an active layer area 1 of the semiconductor device.
Although it is effective to increase the number of fingers in this manner so as to increase the device output, too great and increase in their number increases the chip width, which, in turn, reduces the mechanical strength of the chip. In addition, chip warpage increases due to influence of heat in mounting. For this reason, unit finger length must be increased to achieve high output.
In the prior art, as shown in FIG. 1, the active layer area 1 is uniformly formed with respect to the gate fingers.
Although it is effective to increase the number of fingers as described above so as to increase the device output, the package capacitance undesirably increases, or the chip undesirably warps during assembling. In consideration of these problems, to achieve a high output, the unit finger length may be increased.
Warping of the chip originates from the PHS (Plated Heat Sink) structure in which a thin chip is used, and a thick metal layer is formed on the lower surface of the chip in order to cope with an increase in amount of heat generated as a result of increase in output from the element. That is, since the chip is thin, the chip warps even at room temperature due to the stress incurred by formation of the thick metal layer on the lower surface of the chip. When heat is applied in die bonding, the chip further warps, resulting in chip warpage. The stress of the warpage remains on the chip substrate, posing problems in reliability (e.g., the chip may crack in service due to a thermal shock upon an ON/OFF operation and may break in the worst case).
If the finger length is simply elongated, the decrement in thermal resistance with respect to a given DC power to be supplied becomes small, resulting in an increase in channel temperature.
FIG. 2 shows the relationship between a gate finger length L (.mu.m), a thermal resistance R.theta. (.degree. C./W), and an increment .DELTA.T (.degree.C.) in channel temperature. In FIG. 2, the finger length L (.mu.m) is plotted along the abscissa, and the thermal resistance R.theta. (.degree.C./W) and the increment .DELTA.T (.degree.C.) in channel temperature are plotted along the left and right sides of the ordinate, respectively.
FIG. 2 shows the thermal resistance R.theta. obtained when the finger length is changed in a comb-shaped gate structure having 96 fingers, and the increment (.alpha.T) in channel temperature obtained when a DC power proportional to the gate width at that time is supplied. Note that the DC power is 1 W per unit gate width.
As for the relationship between the finger length L (.mu.m) and the thermal resistance R.theta. (.degree.C./W) on the left side of the ordinate shown in FIG. 2, the thermal resistance can be reduced by increasing the finger length so as to increase the gate width. However, after the finger length reaches a certain value, the thermal resistance begins to decrease non-linearly.
On the other hand, in the relationship between the finger length L (.mu.m) and .DELTA.T (.degree.C.) on the right side of the ordinate, an increase in finger length L increases .DELTA.T (.degree.C.). That is, when a DC power proportional to the gate width is supplied, .DELTA.T undesirably increases with an increase in finger length L, resulting in high channel temperature